About the Role Design and draw the physical analog layout of the cutting-edge analog-to-digital converter chips, and assist CTO to finish the full chip until mass production Responsibilities Assist chip design team to complete physical analog layout Assist chip design team to complete full chip layout design Qualifications Bachelor's degree in electrical engineering, and electronic engineering or related field5+ years of experience in cutting-edge analog chip layout design Experience in complex analog module layout such as ADC, DAC, PLL or RFSo CExperience in top level physical layout design such as Bump map, I/O ring, ESD/latch-up protection and substrate noise reduction techniques Experience in handling DRC, LVS, ERC, ANT, BUMP checks Experienced engineer will be considered as Senior or Principal grade Preferred Skills Experience in precision analog layout design Experience in ultra-high speed clocking layout design Experience in making Pcell Relocation This job may relocate to Shenzhen He Tao Technology Park
