On-site Full Time 5 - 30 Year Mid-Senior level
Skills:
Python
Duties

Microarchitecture and design in Verilog/System Verilog.
Define and own ASIC design methodologies.
Integrate complex IPs developed by internal groups as well as other vendors.
Perform block and chip-level RTL verification and gate-level netlist testing.
Support other ASIC design activities such as Lint, CDC checks, formal verification, synthesis, and DFT.
Assist back-end engineers with timing closure and ECOs.
Chip bring-up, validation, and debugging.
Support Firmware development and Applications teams.

Requirements

BS/MS in Electrical/Computer Engineering.
BS degree with 2+ years of relevant experience, or recent graduate with MS degree.
Knowledge of Verilog/System Verilog, UVM.
Fluent in Verilog and System Verilog.
Good oral and written communication skills.
Knowledge/experience with Python is a plus.
Knowledge of ASIC EDA tools such as Synopsys DC, Cadence Incisive (IES), Verdi, etc., is a plus.

Additional Information
Job Level
Mid-Senior level
Publish Date
08/05/2025
Job Ref. No.
N/A
Job Function
Electrical / Electronic Engineering
Company Overview
Credo is a company with a rich history in Ser Des IP and high-speed interconnect solutions, with multiple R&D centers globally and a strong track record of technological breakthroughs. We are committed to fostering an inclusive culture and providing equal employment opportunities regardless of background or identity.
#J-18808-Ljbffr